Memory devices, such as DRAM cells, that each comprises an access transistor and an adjacent storage trench capacitor in series connection have demonstrated great advantages over conventional planar-stacked device structures. Trench capacitors have replaced the planar storage capacitors in order to meet the scaling demands for high performance dynamic random access memory (DRAM) cell production.
A trench capacitor is a three-dimensional device formed by etching a trench into a semiconductor substrate. After trench etching, a doped region is typically formed in the lower portion of the trench surrounding interior walls of the trench, which serves as an outer electrode or a buried plate electrode of the trench capacitor. A node dielectric is then formed over the outer or buried plate electrode in the trench, which serves as the insulating layer of the trench capacitor, followed by filling the trench, for example, with doped polycrystalline silicon (hereinafter poly-Si), which serves as the inner or upper electrode of the trench capacitor.
In order to isolate the outer electrode or the buried plate electrode of the trench capacitor from the source or drain region of the adjacent transistor, an insulating collar is typically deposited inside the trench on the trench sidewall. The insulating collar inside the trench narrows the trench opening and thus increases the series resistance of the trench capacitor. The increased series resistance impedes the speed of charge transfer to and from the storage trench capacitor and slows down the reading and writing operations.
As the devices are scaled below 90 nm, the thickness of the insulating collar is nevertheless maintained substantially the same, in order to ensure proper electrical isolation between the trench capacitor and the adjacent transistor. Consequentially, the trench resistance is becoming prohibitively high due to the relatively narrower trench opening.
In order to solve the above-described problems, a local oxidation of silicon (LOCOS) process has been used to form a buried LOCOS collar, which is recessed into the trench sidewalls and which therefore does not cause reduction in the trench opening diameter.
However, the buried LOCOS collar so formed has several inherent disadvantages. First, because it is formed by oxidizing the trench sidewall, and because the trench sidewall comprises various crystallographic orientations of different susceptibility to oxidation, the buried LOCOS collar does not have a uniform thickness. Instead, it is characterized by an irregular and non-uniform perimeter. Secondly, the LOCOS process requires multiple depositions of dielectric layers on the trench sidewall, which renders the process very complicated and almost cost-prohibitive. Further, the LOCOS requires removal of sacrificial polysilicon from the trench after formation of the buried LOCOS collar, which may have other deleterious impacts on the device structure, such as, for example, generation of defects and damage of the alignment marks.
There is therefore a continuing need for improved DRAM cells with buried collars that have substantially uniform thickness and are recessed into the trench sidewalls of the trench capacitors. Further, there is a need for a simple and reproducible method of forming such buried collars, with little or no deleterious impact on other parts of the DRAM cells.